Activity
From 08/31/2010 to 09/29/2010
09/27/2010
- JM 04:24 PM FPGA Development: RE: TLK100 Ethernet
- Mike
Just to be sure can you tell me how you pinned out the PCB footprint. Does it match this picture looking from the top or component side of the board?
John - JM 03:57 PM FPGA Development: RE: TLK100 Ethernet
Mike,
After talking this out with our software guy we are convinced its as your said,one of two things. The connection form the TLK100 to the Ethernet or a configuration pullup that configured it wrong on power up. The board does...- MW 03:49 PM FPGA Development: RE: TLK100 Ethernet
- Power up the unit in your board. Stop at u_boot and type:
- JM 02:05 PM FPGA Development: RE: TLK100 Ethernet
- The JTAG R's and connector are not installed.
I have the ethernet connected to my home switch.
I set the Ip address to a fixed value the was not used on my network, that is where the 172.15.1.37 came from. It is not that on... - MW 01:55 PM FPGA Development: RE: TLK100 Ethernet
- Hi John,
It looks like the OMAP MII interface is not making it to your network. The 169.254.X.X network means that the OMAP tried to use DHCP to get a network address, but was unable to find a DHCP server and get a response. After a... - JM 01:12 PM FPGA Development: RE: TLK100 Ethernet
- Here is the ip addrs when plugged into the Critial Link and IT WORKS
Critical Link dev IT WORKS
root@mityomapl138:~# ip addr show
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
link/loopback 00:00:00:00:00:00 brd 00:00:00:... - JM 12:26 PM FPGA Development: RE: TLK100 Ethernet
- I didn't write them down I just typed them when he told me to. This was in u-boot. Once I typed them in I could ping in uboot I didn't get it to work yet in our control board but if I plug it into your development it works fine.
- MW 07:31 AM FPGA Development: RE: TLK100 Ethernet
- What were the software commands? If they involved setting the peripheral configuration in u-Boot, then they only need to be run once (assuming a "config save" was performed).
I guess I'm not sure I understand what you did to fix the ...
09/26/2010
- JM 11:13 PM FPGA Development: RE: TLK100 Ethernet
- Does the Ethernet on the MityDSP need to be initialized for each new TLK100 it gets plugged into? This one was initialized when plugged into one of the Critial Link boards and never reinitialized. When I first plugged it into the Cr...
09/25/2010
- MW 02:27 PM Software Development: RE: Clean Shutdown
- I think the most important thing is to mount the root filesystem and any filesystem you have your executable on with the noatime option, and then remount it as read only after the processor has booted. Ideally, the startup scripts from ...
09/24/2010
- JM 08:34 PM FPGA Development: RE: TLK100 Ethernet
- hey would it be possible that we talk on the phone?
858-254-0008
- MW 08:20 PM FPGA Development: RE: TLK100 Ethernet
- That message is OK. You can set up ethernet to use MII or RMII (but not both, and you're using MII).
It looks like it found the phy via MDIO OK and it is trying to get a dhcp address and failing.
You might try: - JM 08:06 PM FPGA Development: RE: TLK100 Ethernet
- I saw this among the test
EMAC: MII PHY configured, RMII PHY will not be functional
I attached the whole text - MW 07:50 PM FPGA Development: RE: TLK100 Ethernet
- Can you dump out the text from the boot sequence? Does the u-Boot locate the PHY (via the MDIO scan)?
-Mike
- JM 07:42 PM FPGA Development: RE: TLK100 Ethernet
- OK I made all the changes and it still does not work. I now think there are only two difference between out circuits:
1) pull up resistor values mine 4.75K and yours 2.2K
2) I grounded the Ethernet connector shield/cover and you ... - How do you recommend we handle shutdown of our embedded device in order to ensure the consistency of the Linux file system and anything else needed for a clean reboot?
We're doing a device that can be plugged in and unplugged at will.... - WF 12:02 PM Software Development: RE: LCD/Display questions
- We were able to get the LCD going with no problem, BTW. We'll be using it for our demo next week.
Thanks for the help.
09/23/2010
- MW 04:35 PM FPGA Development: RE: TLK100 Ethernet
- yes. you should add a pull-up.
- JM 04:16 PM FPGA Development: RE: TLK100 Ethernet
- Mike,
The green on the component means I used a different value cap or resistor. C216 is there but I used a 1uF ceramic Cap instead of the 0.1uF. I must have saw that in the TLK100 spec otherwise I would not have made it different. ... - MW 03:46 PM FPGA Development: RE: TLK100 Ethernet
- Hi John,
I think you need to tie the RESET line on the phy to the MII_RESET_N signal. The SYS_RESET_N does not get asserted in u-Boot (or the baseline kernel, as neither the SPI or audio device support has been tested and released ye... - JM 03:23 PM FPGA Development: RE: TLK100 Ethernet
- More information for you.
Attached is a comparison between the Critical link schematics and ours schematics. View this in a PDF reader and choose under menu View>Page display>Two Up to see full schematics.
The green shows the diff... - I know this is outside of your support area but I thought I would ask this in case you might have an idea of what to change or check. I appreciate any feedback your hardware guys can give me.
I used the same circuit for the Ethernet ...
09/22/2010
- MW 02:28 PM Software Development: RE: LCD/Display questions
- You'll need a different FPGA image. You also need to load an additional module (for the touchscreen controller on the LCD).
-Mike - WF 02:26 PM Software Development: RE: LCD/Display questions
- Yup. That did it.
For some reason, I had copied the instructions for the Rev. C board instead of the ones above.
Test gradient looks fine now, and so does my logo.
Now we move on to installing the LCD panel (the one we got from ... - MW 02:05 PM Software Development: RE: LCD/Display questions
- Ah. OK. You punched in the i2c commands for the Rev C board. You have 0x3f programmed into position 0x08.
Please use the following two commands (as described in the wiki): - TI 01:53 PM Software Development: RE: LCD/Display questions
- I added a simple test pattern generator to the wiki [[LCD_configuration]]. It draws a white box around the border of the frame buffer and fills it
with 16 bars. Each bar is one bit of color, so you should get 5 blue bars, 6 green bars,... - WF 01:50 PM Software Development: RE: LCD/Display questions
- Done. Here's what I see:
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 4c 01 10 04 00 00 14 64 3f 06 80 00 a9 db 97 22 L???..?d???.???"
10: 00 00 00 00 00 22 e1 5f ac b2 5c 48 41 00 00 00 ....."?_... - MW 08:17 AM Software Development: RE: LCD/Display questions
- After you are up and running, could you please run a
09/21/2010
- WF 04:16 PM Software Development: RE: LCD/Display questions
- Definitely not a Rev C board, so it must be a B (I think we have an A here as well, but this isn't it).
Yes, actually, we do see a Linux prompt and cursor on that screen. Text is blue and the penguin at the upper left is blue and gree... - MW 03:22 PM Software Development: RE: LCD/Display questions
- Can you please confirm the revision of your board (B, or C)?
Before you write to the /dev/fb0 device, do you see a linux prompt? Is the text white (you may need to poke the blank variable as mentioned above). I am concerned about th... - WF 03:13 PM Software Development: RE: LCD/Display questions
- Got it working. A few oddities, but I'm now able to at least talk to the frame buffer.
The screen is all blue and green. Not sure why I don't get any reds. But I won't be using DVI for my real demo, so that's not very critical. Quite ... - TI 10:07 AM Software Development: RE: LCD/Display questions
- William
If you are seeing blue vertical stripes (every other pixel) then the frame buffer is working..
try the following command...
echo 0 > /sys/devices/platform/da8xx_lcdc.0/graphics/fb0/blank
If the screen shows a login prompt, th...
09/20/2010
- WF 10:53 PM Software Development: RE: LCD/Display questions
- OK -- we're definitely making progress here. I now see a raster on the DVI-based monitor. It's just vertical blue stripes, but clearly something is driving a signal out to the display. Yes, the instructions are involved, but they're easy...
- WF 09:37 PM Software Development: RE: LCD/Display questions
- Got it. I'll check this out right now and let you know what happens.
- MW 08:08 PM Software Development: RE: LCD/Display questions
- That's the right image. All the files show up at the bottom of the wiki.
I've updated the wiki with more instructions (they seem involved, but it's not that bad once you do it the first time), primarily with turning on the DVI cont... - WF 02:23 PM Software Development: RE: LCD/Display questions
- I downloaded the file "IndustrialIO_dvi_revA-B.bin" and used it to program the FPGA (in Linux, using the instructions from the Wiki). I then did the configuration commands found on the LCD configuration Wiki page. That seems to have gott...
- WF 11:56 AM Software Development: RE: LCD/Display questions
- We'll take a look at this setup today and let you know what happens.
The next thing we'll want to know is what commands (ioctl, for example) are enabled on the dev/fb device. I assume that the device will have various "files" visible ...
09/17/2010
- MW 06:32 PM Software Development: RE: LCD/Display questions
- It's off the [[Das_U-Boot_Port]] page from the start page. I'll look at making another entry.
- DV 06:06 PM Software Development: RE: LCD/Display questions
- Could you put the link to that wiki page into the wiki start page please.
- MW 05:52 PM Software Development: RE: LCD/Display questions
- The [[LCD configuration]] wiki page has been started that will cover the information you need. It's a work in progress, but there should be enough info in there now to at least force a frame buffer device into existence for the kernel.
- DO 02:27 PM FPGA Development: RE: How to implement bidirectional BLVDS in the FPGA (Spartan-6 )
- I received a reply back from Xilinx tech support.
They indicated that the approach for Spartan-6 would be similar to Virtex-E devices, and pointed me to an app note covering bidirectional BLVDS.
If anyone is interested, the app note ...
09/16/2010
- DV 08:26 PM Software Development: RE: LCD/Display questions
- I'll need a little more information about the uboot to be able to have it tell the kernel to initialize the device. Are we setting some environment variable here?
- MW 07:01 PM Software Development: RE: LCD/Display questions
- Mr. Schlunk,
The kernel included in the development kit provided should have the necessary code installed to support either the DVI interface or the LCD panel interface. To enable the display, the config options in uBoot must be upda... - We are trying to figure out how to get video out of the board and had a couple of questions.
Does your development kit already come with the settings file for the LCD that you sell, and for the DVI adapter? If not, can you tell me how... - I need to implement a data bus as part of an interface to the Xilinx FPGA, and it must be a bidirectional BLVDS interface. I looked in the Xilinx document: Spartan-6 FPGA SelectIO Resources, v1.3.
On p. 37, there is a diagram that descr...
09/07/2010
- MW 04:12 PM FPGA Development: RE: Critical link bit file
- Actually John,
you shouldn't need to reprogram the NAND/root filesystem. Only the kernel. The NAND should still be OK.
-Mike
- MW 04:10 PM FPGA Development: RE: Critical link bit file
- Right. The procedure you just ran only reloads the bootloader images.
You will also need to reload the kernel image and the root filesystem to boot all the way up.
The binary kernel image (uImage) and the jffs2 image for the roo... - JM 04:03 PM FPGA Development: RE: Critical link bit file
- it gets into uboot but once past uboot I get this
8192 KiB M25P64 at 0:0 is now current device
Wrong Image Format for bootm command
ERROR: can't get kernel image!
- JM 04:01 PM FPGA Development: RE: Critical link bit file
- that worked I am backup and running.
thanks
John - MW 03:52 PM FPGA Development: RE: Critical link bit file
- Hi John,
I copied the instructions wrong from our factory programming instruations. Sorry. The "-c" option should have been a "-v" option.
The command should have read: - JM 03:43 PM FPGA Development: RE: Critical link bit file
- I ran this exactly how you said and I get the usage for the command here is what I typed in
sfh_OMAP-L138 -flash -c -p COM1 UBL_SPI_MEM.ais u-boot.bin
John - MW 01:38 PM FPGA Development: RE: Critical link bit file
- Look at the [[Reprogramming a Dead Board]] wiki link. Let me know if you run into trouble.
-Mike
- JM 01:18 PM FPGA Development: RE: Critical link bit file
- It was my fault not yours so no big deal. If you can post what it takes to re-flash the boot code. If this doesn't work I can ship it back to you.
I will make sure to type in verbatim what you show.
thanks
John - MW 07:54 AM FPGA Development: RE: Critical link bit file
- Hi John,
Well, the bad news is that I think you whacked the bootloading code on the SPI FLASH.
The "sf write" command was expecting, I think, a hex arguement for the filesize, and you passed it the decimal equivalent. This told it... - MW 07:57 AM Software Development: RE: Audio help needed
- Hi Otmar,
The API will be ALSA.
My best guess would be something mid-October. We'll try to bump it up on the priority list here.
-Mike
09/03/2010
- JM 06:40 PM FPGA Development: RE: Critical link bit file
- Nothing at all unless I hit both buttons and then I see BOOTME.
here is the console after doing the Kermit upload
U-Boot > loadb 0xc07000000
## Ready for binary (kermit) download to 0x07000000 at 115200 bps...
## Total Size ... - MW 06:35 PM FPGA Development: RE: Critical link bit file
- Do you have a text capture of the commands you typed?
You need to be careful executing commands that write to the NOR, you can correupt the bootloader code....
When you power cycle, do you see anything out of the serial port at all... - JM 06:32 PM FPGA Development: RE: Critical link bit file
OK I went through all of that and now my platform does not boot at all. no text coming across on the serial port.
John- MW 04:14 PM FPGA Development: RE: Critical link bit file
- Sorry, tftp is network transfer protocol. Didn't know you weren't on the network.
If you would like to transfer the data using a serial port, you should be able to a kermit transfer. To load the file via serial type:
loadb 0xC070... - JM 03:47 PM FPGA Development: RE: Critical link bit file
- Why would I have q network cable plugged in and what to I plug it into? My home network? I am using the serial port to connect to the development station.
If I plug it to my home network how to I specify where the file is?
John - MW 03:38 PM FPGA Development: RE: Critical link bit file
- This usually means that the network cable isn't plugged in or the other end isn't talking.
- JM 03:09 PM FPGA Development: RE: Critical link bit file
- When trying to load the FPGA through Uboot I get this error
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No link
T WARN: emac_send_packet: No lin... - JM 02:57 PM FPGA Development: RE: Critical link bit file
- It looks like it works once I tri-stated the wait signals I can not reproduce the problem.
I sent a new file to our software guys to confirm they do not see a problem but I am confident the problem is fixed.
thanks for you help
... - JM 01:22 PM FPGA Development: RE: Critical link bit file
- We only use CS2 and the IO_EMA_D bus is only driven when CS2 and OE are active.
I have the wait signals driven high so this may be the issue I am going to float them and retry thanks. If this doesn't work I will do the other reco... - MW 11:26 AM FPGA Development: RE: Critical link bit file
- Also, if you'd like to send me your project file (offline, if you'd prefer) we could arrange that. Then we can at least review it or try it here.
- MW 11:24 AM FPGA Development: RE: Critical link bit file
- John. Quick question: which chip select space are you using to talk to the FPGA? We have wired all of them over to the FPGA. CS3 is reserved for the NAND interface. Please ensure that CS3, the EMA_D, and EMA_WAIT0 lines are tristate...
- Can you send me the bin and bit file for your FPGA. I am trying to debug the crash that happens when we program our FPGA. I think I have reproduced it on my system and I have confirmed it does no happens If I do not program the FPGA....
08/31/2010
- OS 07:06 PM Software Development: RE: Audio help needed
- Hi Mike,
Thank you for the information.
Once the drivers exist -- would you know what API I should probably be using -- e.g. ALSA or OSS or just fopening the device?
Also, so we can plan things a bit better on our end, is there... - MW 05:20 PM Software Development: RE: Audio help needed
- Hello Mr. Schlunk,
Unfortunately, in order to use the audio output a new sound "board/driver" needs to be written and added to the kernel/sound/soc/davinci section of the linux kernel for the Industrial I/O board. We have started on... - JM 04:08 PM FPGA Development: RE: FPGA Unused Pins
- Thanks
- MW 03:47 PM FPGA Development: RE: FPGA Unused Pins
- Hi John,
In general, you should tri-state / float all unused pins on the FPGA. This will result in those pins behaving the same as when the FPGA is not programmed (e.g., during power up, etc.). Any pins connected between the FPGA an... - Did you have to do anything special to the unused EMIFA pins like
I_EMA_CS0_N
I_EMA_CS3_N
I_EMA_CS5_N
I_EMA_CAS
I_EMA_RAS
I_EMA_SDCKE
I_EMA_RNW
to insure that the FPGA does not interfere with the EMIFA bus?
I have lo... - JM 04:05 PM FPGA Development: RE: Digital DNA
- Yes but I think the range of the DNA value is assigned per customer so each customer has a unique set of values and no other companies can buy the FPGA with those values. At least this is how the Xilinx FAE explained it to me, this wil...
- MW 03:53 PM FPGA Development: RE: Digital DNA
- Stuff you probably already know, but:
According to our distributor, the Xilinx DNA code is unique per chip (like a serial number) and you cannot request codes, they are assigned and burned in at factory. You can access them using the...