Activity
From 08/03/2010 to 09/01/2010
08/31/2010
- OS 07:06 PM Software Development: RE: Audio help needed
- Hi Mike,
Thank you for the information.
Once the drivers exist -- would you know what API I should probably be using -- e.g. ALSA or OSS or just fopening the device?
Also, so we can plan things a bit better on our end, is there... - MW 05:20 PM Software Development: RE: Audio help needed
- Hello Mr. Schlunk,
Unfortunately, in order to use the audio output a new sound "board/driver" needs to be written and added to the kernel/sound/soc/davinci section of the linux kernel for the Industrial I/O board. We have started on... - JM 04:08 PM FPGA Development: RE: FPGA Unused Pins
- Thanks
- MW 03:47 PM FPGA Development: RE: FPGA Unused Pins
- Hi John,
In general, you should tri-state / float all unused pins on the FPGA. This will result in those pins behaving the same as when the FPGA is not programmed (e.g., during power up, etc.). Any pins connected between the FPGA an... - Did you have to do anything special to the unused EMIFA pins like
I_EMA_CS0_N
I_EMA_CS3_N
I_EMA_CS5_N
I_EMA_CAS
I_EMA_RAS
I_EMA_SDCKE
I_EMA_RNW
to insure that the FPGA does not interfere with the EMIFA bus?
I have lo... - JM 04:05 PM FPGA Development: RE: Digital DNA
- Yes but I think the range of the DNA value is assigned per customer so each customer has a unique set of values and no other companies can buy the FPGA with those values. At least this is how the Xilinx FAE explained it to me, this wil...
- MW 03:53 PM FPGA Development: RE: Digital DNA
- Stuff you probably already know, but:
According to our distributor, the Xilinx DNA code is unique per chip (like a serial number) and you cannot request codes, they are assigned and burned in at factory. You can access them using the...
08/30/2010
- I'm trying to figure out a simple method of getting a sound file to play on the board from our app.
After looking around a bit, I'm still not sure what I should be doing. Can anyone point me in the right direction?
- JM 02:36 PM FPGA Development: RE: Accessing the FPGA Memory space using U-boot
- Hey I figured it out so never mind. the FPGA is at 0x6000000 and the memory commands in Uboot seem to work.
- I sent this messge to our software guys also but if youcan help it would be appreciated.
In order to debug the FPGA I need the ability to read and write memory locations. I need some help to get this working on my development stat... - JM 01:37 PM FPGA Development: RE: Digital DNA
- We do no need it on the MityDSP board I was just curious. We are using it on our PROBE FPGA. If you had one assigned it would give us the ability to verify it and confirm that the FPGA is a Critical Link FPGA, another level of security...
08/27/2010
- MW 03:37 PM FPGA Development: RE: Digital DNA
- Hi John,
We're still looking into this here (I wanted to at least get you some feedback that someone saw your post). The immediate answer is, "no we haven't specifically requested a DNA value be assigned".
We haven't used the Digi...
08/26/2010
- Did you get a digital DNA value assigned for your FPGA's?
08/24/2010
- TC 09:11 PM FPGA Development: RE: POWER DOWN Memory Corruption
If your application will not be writing to the NAND flash then you should not need hold-up circuit from the motherboard. However, if you plan to mount a user filesystem rw, and plan to write to it during normal operation, then you may ...- JM 09:04 PM FPGA Development: RE: POWER DOWN Memory Corruption
- So do you think we need to put on our mother board a circuit to hold up the power and interrupt the OMAP to let it know power is going down? Or do you think that your read-only mount will be all that is needed?
thanks for the quick r... - TC 08:58 PM FPGA Development: RE: POWER DOWN Memory Corruption
- John -
We are indeed aware of this and are working on a solution. We plan to allow for the root file system to be mounted as a read-only file system (currently it's mounted read-write). Mounting the root file system read only will al... - Software guys tell me they had a case where the FLASH memory was corrupted when the power was removed at the wrong time. This would be a disaster for us if this happened in the operating room. It sounds like we need to have either a...
- MP 06:51 PM FPGA Development: RE: Programming the FPGA
Hi John.
It looks like you are generating the .BIN file using the bitgen tool ("Generate Programming File" step in ISE), instead of the required iMPACT tool method. While the bitgen tool does in fact generate a .BIN file, it doesn'...- JM 04:00 PM FPGA Development: RE: Programming the FPGA
- Here is the .BGN but there were no .CFI or .PRM files in the FPGA directory.
- MP 03:44 PM FPGA Development: RE: Programming the FPGA
Hi John.
Would you be able to upload the .BGN .CFI & .PRM files that go with the .BIN file you have already uploaded? These are report files that get generated with the .BIT and .BIN files. I suspect there is a problem with a sett...- We are using the MityDSP-L138. Our software guys are not able to program my FPGA bin file using your routine. Your routine only programs the bin file that you provided and does not seem to light the green LED for the BIN file I provide...
08/23/2010
- JP 02:34 PM Software Development: RE: Rescanning the Nand flash
- Dennis,
Just so you know, the suggestions below are not based on personal experience.
Not sure there is a command to do exactly what you are looking for. There is the "nand scrub" command and it comes with a warning:
Warning: sc... - I made a type-o when loading the Nand flash. I managed to convince the flash that it has a whole bunch of bad areas. Is there a utility to tell the system to "delete" all bad areas and rescan the flash to see which are really bad?
08/18/2010
- DV 04:16 PM Software Development: RE: Loading FPGA
- Yes it is an industrial i/o board. That file did load, the light did come on. I need to tell the fpga guys they gave me a bad file. Thank you for the help. I'd recommend posting IndustrialIO.bin on the wiki so your user's can run that te...
- MW 03:46 PM Software Development: RE: Loading FPGA
- If you are using the Industrial I/O board Critical Link provided, try using the file attached below. This file is known to load correctly with your setup. This will eliminate any issues with the FPGA image. The image should be "safe" ...
- DV 03:35 PM Software Development: RE: Loading FPGA
- Sorry about the typo-s. My email/web machine doesn't have a serial port so I've got an old laptop running the hyperterm and have to copy stuff by hand.
tftp:
Load address: 0xc0700000
Loading: #####....
done
Bytes transferr... - JP 03:16 PM Software Development: RE: Loading FPGA
- On the tftp, what is the reported size of the transfer? Something like 0x71544 is expected. If the data is not the right size, the load will not be successful.
This is probably just a typo, but on the tftp, you have "0xc0700000" and o... - DV 03:08 PM Software Development: RE: Loading FPGA
- I did tftp: 0xC0700000 192.168.1.118:fpga.bin
got the ### marks
Did
loadfpga 0xC07000000
no light, message "Loading FPGA Done"
Did (again)
sf probe 0
sf erase 0x580000 0x80000
sf write 0xC0700000 0x58000 ${filesize}
no l... - JP 02:58 PM Software Development: RE: Loading FPGA
- Yes, the "done" LED should light up when the FPGA is programmed correctly.
Can you include the set of commands you are sending and having trouble with?
Thanks.
- DV 02:51 PM Software Development: RE: Loading FPGA
- Should the "done" LED light up if the FPGA was programmed correctly?
- JP 02:39 PM Software Development: RE: Loading FPGA
- Dennis,
You are correct that the write command is missing the offset.
In the setenv command, the read is correct. The steps are to read the image from flash into memory and then load the memory image into the fpga. Two things to n... - I've tried loading the FPGA. I didn't write the FPGA code, I'm just trying to load an fpga.bin file that I've been given. 1) The loadfpga command doesn't give me an error message, but I was told the "done" (d1) LED should come on, it doe...
08/09/2010
- DV 08:57 PM Software Development: RE: Kernel documentation
- Interrupt number 91 (aka IRQ_DA850_RPIINT) works. It works, when I queue a DMA write I get an interrupt when it is complete. Thanks for the pointer about the platform drivers. I've used the primitive "request_mem_region" and "request_irq...
- MW 08:40 PM Software Development: RE: Kernel documentation
- The information you are looking for is in the "OMAP-L138 System Reference Guide":http://www.ti.com/litv/pdf/sprugm7d, in the ARM interrupt controller section (chapter 12). The event you are mapping is defined in the kernel at arch/arm/...
- DV 03:50 PM Software Development: RE: Kernel documentation
- Building the uPP driver. I need to register and interrupt service routine.
To do that I need to know the irq number that is generated. The
documentation cover's which wire is asserted, but not what irq number
that causes the CPU to ge...
08/03/2010
- RB 01:41 PM Software Development: RE: Debugging DSP side with CCS_3.3
- HI Mike,
Here is my about dialog:
!cc3about.png!
When I tried to update to 3.3.82 the installer told me I didn't have a previous installation to update. ??
This version of code composer was not an upgrade and was a version that I... - MW 01:20 PM Software Development: RE: Debugging DSP side with CCS_3.3
- Rich,
I am attaching the CCS version information window from help->about.
!CCSVersionInfo.png!
I just tried to attach here to the DSP with the ARM up and booting (running linux with an active BASH shell). No problems connecting... - RB 01:08 PM Software Development: RE: Debugging DSP side with CCS_3.3
- Hi Mike,
Ok, that doesn't seem to work. I downloaded the update version to install CCS 3.3 v12 and when I ran the update it told me I didn't have any products that could be updated. So I guess I'm out of luck. Don't know what to do next...