Activity
From 02/25/2020 to 03/25/2020
03/25/2020
- EH 12:47 AM Support: RE: Intel OpenVINO with the VDK
- Thanks Mike,
That confirms what I've been thinking about it also, so that is the approach I'll take -- merge the two projects into a VDK BSP.
Thanks, and please stay safe out there in NYC..
- MW 12:12 AM Support: RE: Intel OpenVINO with the VDK
- The FPGA code for the VDK is on github here:
https://github.com/CriticalLink/mitysom5csx-dart-evdk/tree/master/fpga
You want the vdk_single if you are using just one camera interface.
The board_spec.xml is part of an OpenCL BSP,... - EH 12:00 AM Support: RE: Intel OpenVINO with the VDK
- I was looking for the one that is for the current VDK, so it would just have the ARM code.
I do have the code from the VDK files on the wiki. There isn't a 'BSP' there, but there are several versions of the FPGA code.
I guess I was loo...
03/24/2020
- MW 11:54 PM Support: RE: Intel OpenVINO with the VDK
- Hi Ed,
If you are looking for an FPGA project / BSP with VDK + OpenCL architected, I don't have one handy. I only have the reference FPGA project that works with the example ARM programs.
If you need that FPGA project, it should b... - EH 11:25 PM Support: RE: Intel OpenVINO with the VDK
- Mike -- I have several examples of Cyclone V BSP's that incorporate an OpenCL kernel. It would be *VERY* helpful to have a starting "BSP" for the VDK, because then I can use the other examples as a reference and add the OpenCL kernel int...
- EH 03:04 PM Support: RE: Intel OpenVINO with the VDK
- Hey Mike, i've been reading manuals for the past few days, and learned quite a lot.
I see now how the BSP and Kernel fit together -- the BSP can contain a partition where the OpenCL Kernel is inserted.
The BSP can contain all of the co...
03/19/2020
- EH 07:58 PM Support: RE: Intel OpenVINO with the VDK
- I found an interesting reference to a presentation here:
https://www.globallogic.com/wp-content/uploads/2016/10/Combination-of-OpenCL-and-Video-Processing-Design-in-SoC_.pdf
It shows using both together, even multiple kernels. Unfort... - MW 07:51 PM Support: RE: Intel OpenVINO with the VDK
- You can, but you have to implement all of that stuff as part of the "BSP" if you don't want to implement it all in OpenCL (which, for the RAW LVDS inputs, is not possible I don't think).
I have only played around a little with that, a... - EH 06:04 PM Support: RE: Intel OpenVINO with the VDK
- There is one key part that I'm not able to wrap my head around just yet. If you have some knowledge here, it would help greatly.
What I know is that I can write an OpenCL kernel that performs some work. I can write a host program with...
03/18/2020
- EH 04:31 PM Support: RE: Intel OpenVINO with the VDK
- I was just looking through the code on that. I've already cloned the git repo.
I'll use that as a starting point. It won't have any of the code related to the VDK, i.e. the Basler LVDS input logic, and the image processing flow that ... - MW 04:27 PM Support: RE: Intel OpenVINO with the VDK
- Hi Ed:
Have you looked at our OpenCL BSP reference kit for our MitySOM-5CSX DevKit?
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/MitySOM-5CSX_DevKit_OpenCL_BSP
It's a little old, but you could probably adapt/use... - EH 04:20 PM Support: RE: Intel OpenVINO with the VDK
- Michael -- I am currently pursuing the OpenCL approach. It seems the most viable.
We are looking at OpenCL implementations of darknet, so my goal will be to see if/how much of a darknet implementation I could get working on the Cyclon...
03/16/2020
- EH 06:31 PM Support: RE: Intel OpenVINO with the VDK
- I wanted to add this link:
https://software.intel.com/en-us/articles/pipecnn-on-intel-fpga-acceleration-of-machine-learning-workloads
It does not sound like PipeCNN is "fast", but it does appear to meet the spirit of what I am atte... - MW 05:09 PM Support: RE: Intel OpenVINO with the VDK
- I will need to check. I don't think I have one that put aside resources
for the current camera pipeline.
-Mike
On Mon, Mar 16, 2020 at 1:01 PM <redmine@criticallink.com> wrote: - EH 05:01 PM Support: RE: Intel OpenVINO with the VDK
- No, I had not looked at that.
I'll take a look at that as well.
Do you have a BSP for the VDK? Or, that start of one? - MW 04:59 PM Support: RE: Intel OpenVINO with the VDK
- Have you looked into HLS instead of OpenCL? If you are familiar with FPGA
/ Intel / Altara Platform Designer, the HLS converts c++ to VHDL that fits
into that framework fairly easily (compared to making a OpenCL design).
To do OpenCL, ... - EH 04:48 PM Support: RE: Intel OpenVINO with the VDK
- Thank you for the advice Greg.
A hybrid approach does seem to be the best way to approach this, as you describe, a combination of Tensorflow lite and some custom FPGA fabric.
My first goal is to get some OpenCl logic working on my...
03/15/2020
- GG 10:23 PM Support: RE: Intel OpenVINO with the VDK
- Hi Ed,
I understand that Tensorflow Lite being CPU only in this instance seems like it is a deal breaker for you. However, please realize that Tensorflow Lite is a portion of Tensorflow that is focused on inferencing on embedded devi... - EH 08:14 PM Support: RE: Intel OpenVINO with the VDK
- Unfortunately, running tensorflow lite on the ARM core would not meet the goals of the project.
Also, if I recall correctly, Tensorflow is used to train a model. What I am interested in is a way to execute a pre-trained model on the F...
03/11/2020
- GG 10:02 PM Support: RE: Intel OpenVINO with the VDK
- Hi Ed,
Regarding an Arria10 "VDK"or equivalent, the MityCAM-C50000 is an evaluation platform for the CMV50000 CMOS image sensor from ams / CMOSIS. We also have evaluations platforms for some Canon sensors that can be found on https:/... - EH 06:13 PM Support: RE: Intel OpenVINO with the VDK
- Answering my own question -- it looks like this: https://www.criticallink.com/product/mitycam-c50000/
But, I'd still like to know what is possible with the Cyclone V VDK - EH 06:04 PM Support: RE: Intel OpenVINO with the VDK
- You don't by chance have an Arria10 "VDK" or equivalent? What would be the most equivalent solution you have?
- Do you have any information about using the Intel OpenVINO with the VDK?
I know that OpenVINO works with Aria10 devices, but I'm not sure if it is possible to target a Cyclone V -- even as a prototype, reduced complexity board.
I'm...
03/10/2020
- EH 09:42 PM Support: RE: Missing dependencies
- h1. SUCCESS!
I was able to build, on my Ubuntu machine. I just need to add the --host, but the target did not seem to matter. Not sure I fully understand what the option was doing, but I'm able to build a modified demo_app which work... - EH 09:18 PM Support: RE: Missing dependencies
- Oh, I should mention -- I'm trying to build on an Ubuntu host, not on the VDK itself, and just realized that the instructions above are for compiling ON the board, so need to make some adjustments
- EH 09:16 PM Support: RE: Missing dependencies
- So far trying to follow instructions here:
https://support.criticallink.com/redmine/projects/5csx_vdk_basler/wiki/ARM_SW_Architecture_and_Demo_App
Result: - MW 09:02 PM Support: RE: Missing dependencies
- Can you send / post the compiler errors? Which header files are missing?
-Mike
- EH 09:01 PM Support: RE: Missing dependencies
- I have the dev environment setup as per your instructions.
I am familiar with building applications in general.
I'm having a hard time locating the include files I need to build the demo app though.
- MW 06:41 PM Support: RE: Missing dependencies
- Hi Ed,
Sorry about.... on a typical Ubuntu install, I think the only packages you need to install would be "build-essential". The SDK installation (self-extractor) will install a copy of all of the cross-compiler build tools at that ... - On this page: https://support.criticallink.com/redmine/projects/5csx_vdk_basler/wiki/Setting_Up_A_Build_Environment
There is a list of dependencies for linux installation. The wiki reads like this: - A lot of this information is quite out of date... I'm really shooting in the dark wondering if I can get this to work.
My goal is to:
- build some custom FPGA code, using a combination of Verilog/VHDL and OpenCL
- Integrate this int...