{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1552319695267 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552319695272 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 11 16:54:55 2019 " "Processing started: Mon Mar 11 16:54:55 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552319695272 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319695272 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319695272 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1552319695946 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1552319695946 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bufdif.v 2 2 " "Found 2 design units, including 2 entities, in source file bufdif.v" { { "Info" "ISGN_ENTITY_NAME" "1 bufdif_iobuf_in_6pi " "Found entity 1: bufdif_iobuf_in_6pi" {  } { { "bufdif.v" "" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/bufdif.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1552319704657 ""} { "Info" "ISGN_ENTITY_NAME" "2 bufdif " "Found entity 2: bufdif" {  } { { "bufdif.v" "" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/bufdif.v" 91 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1552319704657 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319704657 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/clock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1552319704661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319704661 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Found entity 1: PLL" {  } { { "PLL.v" "" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/PLL.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1552319704665 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319704665 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll/pll_0002.v 1 1 " "Found 1 design units, including 1 entities, in source file pll/pll_0002.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL_0002 " "Found entity 1: PLL_0002" {  } { { "PLL/PLL_0002.v" "" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/PLL/PLL_0002.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1552319704669 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319704669 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1552319704704 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL PLL:inst5 " "Elaborating entity \"PLL\" for hierarchy \"PLL:inst5\"" {  } { { "clock.bdf" "inst5" { Schematic "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/clock.bdf" { { 176 216 376 320 "inst5" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319704715 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_0002 PLL:inst5\|PLL_0002:pll_inst " "Elaborating entity \"PLL_0002\" for hierarchy \"PLL:inst5\|PLL_0002:pll_inst\"" {  } { { "PLL.v" "pll_inst" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/PLL.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319704717 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\"" {  } { { "PLL/PLL_0002.v" "altera_pll_i" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/PLL/PLL_0002.v" 85 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319704751 ""}
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" {  } {  } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1552319704753 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\"" {  } { { "PLL/PLL_0002.v" "" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/PLL/PLL_0002.v" 85 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319704753 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i " "Instantiated megafunction \"PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 100.0 MHz " "Parameter \"reference_clock_frequency\" = \"100.0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode direct " "Parameter \"operation_mode\" = \"direct\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 25.000000 MHz " "Parameter \"output_clock_frequency0\" = \"25.000000 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type General " "Parameter \"pll_type\" = \"General\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1552319704753 ""}  } { { "PLL/PLL_0002.v" "" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/PLL/PLL_0002.v" 85 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1552319704753 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bufdif bufdif:inst " "Elaborating entity \"bufdif\" for hierarchy \"bufdif:inst\"" {  } { { "clock.bdf" "inst" { Schematic "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/clock.bdf" { { 16 216 448 112 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319704762 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bufdif_iobuf_in_6pi bufdif:inst\|bufdif_iobuf_in_6pi:bufdif_iobuf_in_6pi_component " "Elaborating entity \"bufdif_iobuf_in_6pi\" for hierarchy \"bufdif:inst\|bufdif_iobuf_in_6pi:bufdif_iobuf_in_6pi_component\"" {  } { { "bufdif.v" "bufdif_iobuf_in_6pi_component" { Text "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/bufdif.v" 106 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319704769 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "POW_EN_A GND " "Pin \"POW_EN_A\" is stuck at GND" {  } { { "clock.bdf" "" { Schematic "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/clock.bdf" { { 344 248 424 360 "POW_EN_A" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1552319705162 "|clock|POW_EN_A"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1552319705162 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "6 0 1 0 0 " "Adding 6 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1552319705360 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552319705360 ""}
{ "Warning" "WCAL_CAL_GENERIC_RBCGEN_AUTO_GENERIC_PLL_RST" "RST PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll " "RST port on the PLL is not properly connected on instance PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { { "Info" "ICAL_CAL_GENERIC_RBCGEN_AUTO_RBCGEN_CONNECTED_CONNECTION_SUB_INFO" "" "Must be connected" {  } {  } 0 0 "Must be connected" 0 0 "Design Software" 0 -1 1552319705405 ""}  } { { "altera_pll.v" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altera_pll.v" 748 -1 0 } }  } 0 0 "%1!s! port on the PLL is not properly connected on instance %2!s!. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." 0 0 "Analysis & Synthesis" 0 -1 1552319705405 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1552319705459 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1552319705459 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1552319705459 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1552319705459 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4840 " "Peak virtual memory: 4840 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552319705499 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 11 16:55:05 2019 " "Processing ended: Mon Mar 11 16:55:05 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552319705499 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552319705499 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552319705499 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1552319705499 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1552319706924 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552319706930 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 11 16:55:06 2019 " "Processing started: Mon Mar 11 16:55:06 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552319706930 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1552319706930 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock " "Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1552319706930 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1552319707093 ""}
{ "Info" "0" "" "Project  = clock" {  } {  } 0 0 "Project  = clock" 0 0 "Fitter" 0 0 1552319707093 ""}
{ "Info" "0" "" "Revision = clock" {  } {  } 0 0 "Revision = clock" 0 0 "Fitter" 0 0 1552319707093 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1552319707231 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1552319707231 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "clock 5CSXFC6C6U23I7 " "Selected device 5CSXFC6C6U23I7 for design \"clock\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1552319707259 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1552319707307 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1552319707307 ""}
{ "Warning" "WCAL_CAL_GENERIC_RBCGEN_AUTO_GENERIC_PLL_RST" "RST PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll " "RST port on the PLL is not properly connected on instance PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { { "Info" "ICAL_CAL_GENERIC_RBCGEN_AUTO_RBCGEN_CONNECTED_CONNECTION_SUB_INFO" "" "Must be connected" {  } {  } 0 0 "Must be connected" 0 0 "Design Software" 0 -1 1552319707402 ""}  } { { "altera_pll.v" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altera_pll.v" 748 -1 0 } }  } 0 0 "%1!s! port on the PLL is not properly connected on instance %2!s!. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." 0 0 "Fitter" 0 -1 1552319707402 ""}
{ "Warning" "WCUT_CUT_GENERIC_PLL_LOCKED_MISSING" "LOCKED FBOUTCLK PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll " "LOCKED port on the PLL is not properly connected on instance \"PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "%1!s! port on the PLL is not properly connected on instance \"%3!s!\". The %1!s! port on the PLL should be connected when the %2!s! port is connected. Although it is unnecessary to connect the %1!s! signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." 0 0 "Fitter" 0 -1 1552319707417 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1552319707794 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1552319708123 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1552319718839 ""}
{ "Info" "ICCLK_CLOCKS_TOP" "1  (1 global) " "Promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[0\]~CLKENA0 1 global CLKCTRL_G11 " "PLL:inst5\|PLL_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[0\]~CLKENA0 with 1 fanout uses global clock CLKCTRL_G11" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1552319718877 ""}  } {  } 0 11178 "Promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1552319718877 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1552319718877 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "clock.sdc " "Synopsys Design Constraints File file not found: 'clock.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1552319719557 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1552319719558 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1552319719558 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1552319719559 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319719559 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319719559 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319719559 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1552319719559 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1552319719560 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1552319719560 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1552319719560 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1552319719563 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1552319719563 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1552319719564 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1552319719564 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1552319719564 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1552319719564 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1552319719564 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1552319719564 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1552319719564 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1552319719603 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1552319725238 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1552319725334 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1552319725812 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1552319726168 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1552319726318 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1552319726318 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1552319726989 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y23 X10_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y23 to location X10_Y34" {  } { { "loc" "" { Generic "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y23 to location X10_Y34"} { { 12 { 0 ""} 0 23 11 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1552319730961 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1552319730961 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1552319731195 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1552319731195 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1552319731195 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1552319731200 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1552319732095 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1552319732135 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1552319732423 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1552319732423 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1552319733335 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1552319735789 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/output_files/clock.fit.smsg " "Generated suppressed messages file C:/Users/User/Desktop/FPGA programs/MitySOM/prova_clock/output_files/clock.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1552319736090 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6624 " "Peak virtual memory: 6624 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552319736778 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 11 16:55:36 2019 " "Processing ended: Mon Mar 11 16:55:36 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552319736778 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552319736778 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:54 " "Total CPU time (on all processors): 00:00:54" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552319736778 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1552319736778 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1552319738046 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552319738050 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 11 16:55:37 2019 " "Processing started: Mon Mar 11 16:55:37 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552319738050 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1552319738050 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock " "Command: quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1552319738050 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1552319738867 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1552319743898 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4856 " "Peak virtual memory: 4856 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552319744318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 11 16:55:44 2019 " "Processing ended: Mon Mar 11 16:55:44 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552319744318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552319744318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552319744318 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1552319744318 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1552319745045 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1552319745805 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552319745810 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 11 16:55:45 2019 " "Processing started: Mon Mar 11 16:55:45 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552319745810 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1552319745810 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta clock -c clock " "Command: quartus_sta clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1552319745810 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1552319745970 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1552319746762 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1552319746762 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319746810 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319746810 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "clock.sdc " "Synopsys Design Constraints File file not found: 'clock.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1552319747336 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319747336 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 10.000 -waveform \{0.000 5.000\} -name CLOCKp CLOCKp " "create_clock -period 10.000 -waveform \{0.000 5.000\} -name CLOCKp CLOCKp" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1552319747336 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|refclkin\} -divide_by 2 -multiply_by 6 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\} " "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|refclkin\} -divide_by 2 -multiply_by 6 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1552319747336 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|vco0ph\[0\]\} -divide_by 12 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\} " "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|vco0ph\[0\]\} -divide_by 12 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1552319747336 ""}  } {  } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1552319747336 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319747337 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1552319747337 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319747337 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319747337 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319747337 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552319747337 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1552319747338 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552319747338 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1552319747338 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1552319747345 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319747347 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319747357 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319747360 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319747363 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319747366 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319747371 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319747371 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319747371 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.978               0.000 CLOCKp  " "    4.978               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319747371 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319747371 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" {  } {  } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1552319747375 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1552319747403 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1552319748634 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319748716 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319748716 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319748716 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552319748716 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552319748716 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319748718 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319748724 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319748726 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319748729 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319748732 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319748735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319748735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319748735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.972               0.000 CLOCKp  " "    4.972               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319748735 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319748735 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1552319748780 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1552319749055 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1552319749580 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319749625 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319749625 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319749625 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552319749625 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552319749626 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749630 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749668 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749672 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749675 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749678 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749678 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749678 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.972               0.000 CLOCKp  " "    4.972               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749678 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319749678 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" {  } {  } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1552319749708 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319749853 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319749853 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552319749853 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552319749853 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552319749853 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749857 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749860 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749863 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552319749866 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749869 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749869 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749869 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.989               0.000 CLOCKp  " "    4.989               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552319749869 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552319749869 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1552319751077 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1552319751077 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5180 " "Peak virtual memory: 5180 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552319751139 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 11 16:55:51 2019 " "Processing ended: Mon Mar 11 16:55:51 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552319751139 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552319751139 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552319751139 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1552319751139 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Quartus Prime Full Compilation was successful. 0 errors, 12 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1552319751891 ""}
