{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1552380533044 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552380533049 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 12 09:48:52 2019 " "Processing started: Tue Mar 12 09:48:52 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552380533049 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1552380533049 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta clock -c clock " "Command: quartus_sta clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1552380533049 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1552380533225 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1552380534025 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1552380534025 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380534073 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380534073 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "clock.sdc " "Synopsys Design Constraints File file not found: 'clock.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1552380534588 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380534588 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 10.000 -waveform \{0.000 5.000\} -name CLOCKp CLOCKp " "create_clock -period 10.000 -waveform \{0.000 5.000\} -name CLOCKp CLOCKp" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1552380534589 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|refclkin\} -divide_by 2 -multiply_by 6 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\} " "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|refclkin\} -divide_by 2 -multiply_by 6 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1552380534589 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|vco0ph\[0\]\} -divide_by 12 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\} " "create_generated_clock -source \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|vco0ph\[0\]\} -divide_by 12 -duty_cycle 50.00 -name \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\} \{inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER\|divclk\}" {  } {  } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1552380534589 ""}  } {  } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1552380534589 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380534589 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1552380534589 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380534590 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380534590 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380534590 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552380534590 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1552380534590 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552380534590 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1552380534590 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1552380534604 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380534606 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380534629 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380534640 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380534646 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380534653 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380534658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380534658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380534658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.978               0.000 CLOCKp  " "    4.978               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380534658 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380534658 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" {  } {  } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1552380534665 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1552380534701 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1552380535999 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380536081 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380536081 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380536081 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552380536081 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552380536082 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380536083 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380536095 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380536101 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380536117 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380536123 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380536143 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380536143 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380536143 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.972               0.000 CLOCKp  " "    4.972               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380536143 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380536143 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1552380536160 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1552380536411 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1552380536960 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380537004 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380537004 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380537004 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552380537004 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552380537004 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537010 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537016 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537022 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537029 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.972               0.000 CLOCKp  " "    4.972               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537034 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380537034 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" {  } {  } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1552380537040 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380537206 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_OUTPUT_COUNTER  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380537206 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~PLL_REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1552380537206 ""}  } {  } 0 332097 "The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network." 0 0 "Timing Analyzer" 0 -1 1552380537206 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1552380537206 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537213 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537218 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537242 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1552380537259 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.666 " "Worst-case minimum pulse width slack is 1.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\]  " "    1.666               0.000 inst5\|pll_inst\|altera_pll_i\|general\[0\].gpll~FRACTIONAL_PLL\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.989               0.000 CLOCKp  " "    4.989               0.000 CLOCKp " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1552380537285 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1552380537285 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1552380538544 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1552380538544 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5180 " "Peak virtual memory: 5180 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552380538634 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 12 09:48:58 2019 " "Processing ended: Tue Mar 12 09:48:58 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552380538634 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552380538634 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552380538634 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1552380538634 ""}
