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["J701",null,"Status","Where"]
[]
["1, 2, 15, 16, 29, 30, 31, 32, 49, 50","GND","connected","GND"]
[4,"FPGA_IO_48_P","open","TP"]
[14,"FPGA_IO_38_P","open","TP"]
[17,"DIN","connected","codec"]
[18,"ACLKR","connected","codec"]
[19,"DOUT","connected","codec"]
[20,"AFSR","connected","codec"]
[21,"AXR9","open","TP"]
[22,"AXR12","open","TP"]
[23,"OMAP_GP0_3","connected","CS1"]
[24,"OMAP_GP0_2","open","3R"]
[25,"OMAP_GP0_0","connected","CS0"]
[26,"MCLK","connected","codec"]
[27,"I2C_SDA","connected","codec, DAC"]
[28,"I2C_SCL","connected","codec, DAC"]
["33,34,35,36","-12V","open","TP"]
["37,38,39,40","+3.3V","connected","U902"]
["41,42,43,44","+5.0V","connected","regs, adc, dac"]
["45,46,47,48","+12V","open","KX3"]
[]
[]
["J700"]
[]
["1, 2, 3, 4, 44, 46, 47, 48 , 49, 50","GND","connected","GND"]
["5, 6, 7, 8 ","+3.3V","connected","U902"]
[11,"SCLK","connected","U901"]
[13,"SIMO","connected","U901"]
[15,"SOMI","connected","U902"]
[]
["J702"]
[]
["1, 2, 49, 50","GND","connected","GND"]
[3,"FPGA_IO_36_N","open","TP"]
[5,"FPGA_IO_34_N","open","TP"]
[9,"FPGA_IO_30_N","open","TP"]
[11,"FPGA_IO_28_N","open","TP"]
[15,"FPGA_IO_24_N","open","TP"]
[17,"FPGA_IO_22_N","open","TP"]
[19,"FPGA_IO_47_N","open","TP"]
[21,"FPGA_IO_45_N","connected","codec_rst","pulled to 3.3"]
[23,"FPGA_IO_43_N","open","spare cs"]
[25,"FPGA_IO_41_N","connected","rx_ps_en","pulled to 5.0","open cut trace"]
[27,"FPGA_IO_39_N","open","TP802"]
[28,"FPGA_IO_39_P","open","TP800"]
[29,"FPGA_IO_33_N","open","TP803"]
[30,"FPGA_IO_33_P","open","TP801"]
[36,"FPGA_IO_23_P","open","TP709"]
[40,"FPGA_IO_11_P","open","TP710"]
[42,"FPGA_IO_13_P","open","J1100"]
[44,"FPGA_IO_15_P","open","J1100"]
[46,"FPGA_IO_17_P","open","J1100"]