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/*
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* Critical Link MityOMAP-L138 SoM Baseboard initializtaion file
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/usb/musb.h>
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#include <linux/mtd/partitions.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/setup.h>
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#include <mach/mux.h>
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#include <mach/da8xx.h>
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#include <linux/can/platform/mcp251x.h>
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#define BASEBOARD_NAME "System9000 Baseboard version 0.7"
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/*
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* 12/16/13 Added SPI1_FPGA_CS_N, commented out GPIO(6,2) in sys9000_gpio_pins
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* Added arrays for SPI1 bus to 9000FPGA
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*/
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#define SPI1_FLASH_CS_N GPIO_TO_PIN(2, 15) // System configuration flash (optional)
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#define SPI1_FPGA_CS_N GPIO_TO_PIN(6, 2) // SOM to FPGA SPI1 cs
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/*
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* GPIO pins
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*/
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static short sys9000_gpio_pins[] __initdata = {
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DA850_GPIO0_1, // SYNC_PLL_CLK2_LOS
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DA850_GPIO0_3, // SYNC_PLL_LOL
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DA850_GPIO0_5, // SYNC_PLL_CLK1_LOS
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DA850_GPIO0_7, // SYNC_MASTER_EN
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DA850_GPIO0_8, // SOM_GP0_8
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DA850_GPIO0_9, // TEST_LED_0
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DA850_GPIO0_10, // SYS_GOOD_LED_YEL
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DA850_GPIO0_11, // SYS_GOOD_LED_GRN
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DA850_GPIO0_12, // SYNC_LED_YEL
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DA850_GPIO0_13, // SYNC_LED_GRN
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DA850_GPIO0_14, // REC_LED_RED
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DA850_GPIO0_15, // REC_LED_GRN
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// DA850_GPIO1_4, // TEST_POINT_1 ...I2C0, needed for voltage regulator
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// DA850_GPIO1_5, // TEST_POINT_0 ...I2C0
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DA850_GPIO4_0, // VCAL_EN
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DA850_GPIO4_1, // VCAL_EN_n
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DA850_GPIO4_2, // ECAL_EN_n
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DA850_GPIO4_3, // ECAL_EN_n
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DA850_GPIO4_4, // VCAL_ZERO
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DA850_GPIO4_5, // VCAL_OUT_EN
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DA850_GPIO4_6, // VCAL_SPARE
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DA850_GPIO4_7, // SSD_DET_N
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DA850_GPIO5_14, // TEST_LED_1
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DA850_GPIO6_0, // SOM_GP6_0
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DA850_GPIO6_1, // SOM_GP6_1
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DA850_GPIO6_2, // SOM_GP6_2, fpga spi cs
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DA850_GPIO6_3, // SOM_GP6_3
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DA850_GPIO6_4, // SOM_GP6_4
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DA850_GPIO6_6, // SOM_GP6_6
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DA850_GPIO6_7, // SOM_GP6_7
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DA850_GPIO6_8, // SOM_GP6_8
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DA850_GPIO6_9, // SOM_GP6_9
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DA850_GPIO6_10, // SOM_GP6_10
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DA850_GPIO6_11, // SOM_GP6_11
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DA850_GPIO7_0, // LDAC0_n
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DA850_GPIO7_1, // LDAC1_n
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DA850_GPIO7_2, // LDAC2_n
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DA850_GPIO7_3, // LDAC3_n
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DA850_GPIO7_4, // LDAC4_n
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DA850_GPIO7_5, // LDAC5_n
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DA850_GPIO7_6, // LDAC6_n
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DA850_GPIO7_8, // CARD_DET3
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DA850_GPIO7_9, // CARD_DET2
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DA850_GPIO7_10, // CARD_DET1
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DA850_GPIO7_11, // CARD_DET0
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DA850_GPIO7_12, // DIO_0_OUT
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DA850_GPIO7_13, // DIO_0_IN
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DA850_GPIO7_14, // DIO_1_OUT
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DA850_GPIO7_15, // DIO_1_IN
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DA850_GPIO8_8, // SYS_RST_N
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DA850_GPIO8_10, // Factory Reset In
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DA850_GPIO8_12, // HW_REV_0
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DA850_GPIO8_13, // HW_REV_1
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DA850_GPIO8_14, // HW_REV_2
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DA850_GPIO8_15, // HW_REV_3
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-1,
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};
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/*
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* SPI Devices:
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* SPI1_CS1: Flash M25PE80
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*/
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static struct mtd_partition sys9000_spi_flash_partitions[] = {
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[0] = {
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.name = "sys9000_fpga",
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.offset = 0,
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.size = SZ_4M,
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},
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[1] = {
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.name = "sys9000_extra",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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// Copied from board-mityomapl138.c in this directory
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static struct flash_platform_data sys9000_spi_flash_data = {
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.name = "m25p80",
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.parts = sys9000_spi_flash_partitions,
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.nr_parts = ARRAY_SIZE(sys9000_spi_flash_partitions),
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.type = "m25p64-nonjedec",
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};
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static struct davinci_spi_config spi_M25PE80_config = {
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.io_type = SPI_IO_TYPE_DMA,
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.c2tdelay = 8,
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.t2cdelay = 8,
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};
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// Added 12/16/13 SPI1 interface to Sys9000 FPGA
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static struct davinci_spi_config spi_9000FPGA_config = {
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.io_type = SPI_IO_TYPE_DMA, // restored 04/21/14
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// .io_type = SPI_IO_TYPE_POLL, // Changed 02/11/14
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.c2tdelay = 0,
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.t2cdelay = 0,
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};
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static struct spi_board_info sys9000_spi1_info[] = {
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[0] = {
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.modalias = "m25p80",
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.platform_data = &sys9000_spi_flash_data,
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.controller_data = &spi_M25PE80_config,
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.mode = SPI_MODE_0,
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.max_speed_hz = 30000000,
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.bus_num = 1,
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.chip_select = 1,
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},
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// Added 12/16/13 user space spidev for SPI2 Cs2
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// Removed 04/21/14
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// [1] = {
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// .modalias = "spidev",
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// .controller_data = &spi_9000FPGA_config,
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// .max_speed_hz = 33000000,
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// .bus_num = 1,
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// .chip_select = 2,
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// },
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};
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// Added 12/16/13 SPI1_FPGA_CS_N
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static u8 spi1_cs[] = {
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SPI_INTERN_CS,
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SPI1_FLASH_CS_N,
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// SPI1_FPGA_CS_N // removed 04/21/14
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};
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static void __init baseboard_setup_spi(void)
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{
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int ret;
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ret = gpio_request(SPI1_FLASH_CS_N, "Sys9000 SPI1 FLASH CS1\n");
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if (ret)
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pr_warning("%s: can not open Sys9000 Flash SPI CS %d\n", __func__, SPI1_FLASH_CS_N);
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// Removed 04/21/14
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// ret = gpio_request(SPI1_FPGA_CS_N, "Sys9000 SPI1 Sys9000FPGA CS\n");
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// if (ret)
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// pr_warning("%s: can not open Sys9000FPGASPI CS %d\n", __func__, SPI1_FPGA_CS_N);
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ret = spi_register_board_info(sys9000_spi1_info,
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ARRAY_SIZE(sys9000_spi1_info));
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if (ret)
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pr_warning("%s: Unable to register SPI1 Info: %d\n", __func__,
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ret);
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}
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static int __init baseboard_pre_init(void)
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{
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pr_info("%s: Entered\n", __func__);
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da8xx_spi_pdata[1].chip_sel = spi1_cs;
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da8xx_spi_pdata[1].num_chipselect = ARRAY_SIZE(spi1_cs);
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davinci_soc_info.emac_pdata->phy_id = "0:03";
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return 0;
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}
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postcore_initcall_sync(baseboard_pre_init);
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static int __init baseboard_init(void)
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{
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pr_info("%s [%s]...\n", __func__, BASEBOARD_NAME);
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davinci_cfg_reg_list(sys9000_gpio_pins);
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baseboard_setup_spi();
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return 0;
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}
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arch_initcall_sync(baseboard_init);
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