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/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include "common_def.h"
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#include <asm/arch/hardware.h>
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#define MUX_CFG(value, offset) \
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__raw_writel(value, (CTRL_BASE + offset));
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/* PAD Control Fields */
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#define SLEWCTRL (0x1 << 6)
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#define RXACTIVE (0x1 << 5)
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#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
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#define PULLUDEN (0x0 << 3) /* Pull up enabled */
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#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
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#define MODE(val) val
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#define DEV_ON_BASEBOARD 0
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#define DEV_ON_DGHTR_BRD 1
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/*
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* PAD CONTROL OFFSETS
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* Field names corresponds to the pad signal name
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*/
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struct pad_signals {
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int gpmc_ad0;
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int gpmc_ad1;
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int gpmc_ad2;
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int gpmc_ad3;
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int gpmc_ad4;
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int gpmc_ad5;
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int gpmc_ad6;
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int gpmc_ad7;
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int gpmc_ad8;
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int gpmc_ad9;
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int gpmc_ad10;
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int gpmc_ad11;
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int gpmc_ad12;
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int gpmc_ad13;
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int gpmc_ad14;
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int gpmc_ad15;
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int gpmc_a0;
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int gpmc_a1;
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int gpmc_a2;
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int gpmc_a3;
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int gpmc_a4;
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int gpmc_a5;
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int gpmc_a6;
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int gpmc_a7;
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int gpmc_a8;
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int gpmc_a9;
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int gpmc_a10;
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int gpmc_a11;
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int gpmc_wait0;
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int gpmc_wpn;
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int gpmc_be1n;
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int gpmc_csn0;
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int gpmc_csn1;
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int gpmc_csn2;
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int gpmc_csn3;
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int gpmc_clk;
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int gpmc_advn_ale;
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int gpmc_oen_ren;
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int gpmc_wen;
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int gpmc_be0n_cle;
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int lcd_data0;
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int lcd_data1;
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int lcd_data2;
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int lcd_data3;
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int lcd_data4;
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int lcd_data5;
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int lcd_data6;
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int lcd_data7;
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int lcd_data8;
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int lcd_data9;
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int lcd_data10;
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int lcd_data11;
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int lcd_data12;
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int lcd_data13;
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int lcd_data14;
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int lcd_data15;
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int lcd_vsync;
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int lcd_hsync;
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int lcd_pclk;
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int lcd_ac_bias_en;
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int mmc0_dat3;
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int mmc0_dat2;
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int mmc0_dat1;
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int mmc0_dat0;
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int mmc0_clk;
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int mmc0_cmd;
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int mii1_col;
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int mii1_crs;
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int mii1_rxerr;
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int mii1_txen;
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int mii1_rxdv;
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int mii1_txd3;
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int mii1_txd2;
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int mii1_txd1;
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int mii1_txd0;
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int mii1_txclk;
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int mii1_rxclk;
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int mii1_rxd3;
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int mii1_rxd2;
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int mii1_rxd1;
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int mii1_rxd0;
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int rmii1_refclk;
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int mdio_data;
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int mdio_clk;
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int spi0_sclk;
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int spi0_d0;
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int spi0_d1;
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int spi0_cs0;
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int spi0_cs1;
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int ecap0_in_pwm0_out;
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int uart0_ctsn;
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int uart0_rtsn;
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int uart0_rxd;
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int uart0_txd;
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int uart1_ctsn;
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int uart1_rtsn;
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int uart1_rxd;
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int uart1_txd;
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int i2c0_sda;
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int i2c0_scl;
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int mcasp0_aclkx;
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int mcasp0_fsx;
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int mcasp0_axr0;
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int mcasp0_ahclkr;
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int mcasp0_aclkr;
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int mcasp0_fsr;
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int mcasp0_axr1;
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int mcasp0_ahclkx;
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int xdma_event_intr0;
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int xdma_event_intr1;
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int nresetin_out;
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int porz;
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int nnmi;
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int osc0_in;
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int osc0_out;
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int rsvd1;
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int tms;
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int tdi;
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int tdo;
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int tck;
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int ntrst;
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int emu0;
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int emu1;
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int osc1_in;
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int osc1_out;
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int pmic_power_en;
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int rtc_porz;
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int rsvd2;
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int ext_wakeup;
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int enz_kaldo_1p8v;
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int usb0_dm;
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int usb0_dp;
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int usb0_ce;
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int usb0_id;
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int usb0_vbus;
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int usb0_drvvbus;
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int usb1_dm;
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int usb1_dp;
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int usb1_ce;
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int usb1_id;
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int usb1_vbus;
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int usb1_drvvbus;
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int ddr_resetn;
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int ddr_csn0;
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int ddr_cke;
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int ddr_ck;
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int ddr_nck;
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int ddr_casn;
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int ddr_rasn;
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int ddr_wen;
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int ddr_ba0;
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int ddr_ba1;
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int ddr_ba2;
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int ddr_a0;
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int ddr_a1;
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int ddr_a2;
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int ddr_a3;
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int ddr_a4;
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int ddr_a5;
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int ddr_a6;
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int ddr_a7;
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int ddr_a8;
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int ddr_a9;
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int ddr_a10;
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int ddr_a11;
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int ddr_a12;
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int ddr_a13;
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int ddr_a14;
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int ddr_a15;
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int ddr_odt;
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int ddr_d0;
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int ddr_d1;
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int ddr_d2;
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int ddr_d3;
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int ddr_d4;
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int ddr_d5;
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int ddr_d6;
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int ddr_d7;
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int ddr_d8;
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int ddr_d9;
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int ddr_d10;
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int ddr_d11;
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int ddr_d12;
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int ddr_d13;
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int ddr_d14;
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int ddr_d15;
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int ddr_dqm0;
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int ddr_dqm1;
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int ddr_dqs0;
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int ddr_dqsn0;
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int ddr_dqs1;
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int ddr_dqsn1;
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int ddr_vref;
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int ddr_vtp;
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int ddr_strben0;
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int ddr_strben1;
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int ain7;
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int ain6;
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int ain5;
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int ain4;
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int ain3;
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int ain2;
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int ain1;
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int ain0;
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int vrefp;
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int vrefn;
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};
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struct module_pin_mux {
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short reg_offset;
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unsigned char val;
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};
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struct evm_pin_mux {
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struct module_pin_mux *mod_pin_mux;
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unsigned short profile;
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};
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#define PAD_CTRL_BASE 0x800
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#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
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(PAD_CTRL_BASE))->x)
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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#endif
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//{sandia_pin_mux, PROFILE_ALL},
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static struct module_pin_mux sandia_pin_mux[] = {
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{OFFSET(gpmc_a4), MODE(7)}, /* lcd enable */
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{OFFSET(gpmc_a5), MODE(7)}, /* USRLED0 */
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{OFFSET(gpmc_a6), MODE(7)}, /* USRLED1 */
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{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, /* touchscreen interrupt */
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//{OFFSET(mcasp0_aclkx), MODE(1)}, /* LCD PWM,ehrpwm0A_mux0, check in other files */
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/* {OFFSET(gpmc_a9), (MODE(7))}; */
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux i2c1_pin_mux[] = {
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{OFFSET(mii1_crs), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(mii1_rxerr), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux i2c2_pin_mux[] = {
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{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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#ifndef CONFIG_NO_ETH
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux rgmii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
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{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
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{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
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{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
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{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
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{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
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{OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */
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{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
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{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
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{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */
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{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
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{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{OFFSET(mii1_rxclk), MODE(7) | PULLUP_EN | PULLUDEN}, /* PHY RESET N on MITYARM3359 EVM */
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{-1},
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};
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static struct module_pin_mux mii1_pin_mux[] = {
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{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux rmii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
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{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
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{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
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{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
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{-1},
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};
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#endif
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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#ifndef CONFIG_AM335X_TF
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//dmckinley moved wp and cd to new pins for sandia
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{OFFSET(gpmc_a3), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC0_WP, 0 = NO WRITE PROTECT */
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{OFFSET(gpmc_a1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD, 0 = CARD DETECT */
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// {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, /* MMC0_WP */
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//{OFFSET(mii1_txen), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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#endif /* CONFIG_AM335X_TF */
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{-1},
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};
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static struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{OFFSET(uart1_rxd), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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{OFFSET(mcasp0_fsx), (MODE(4) | RXACTIVE)}, /* MMC1_CD */
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{-1},
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};
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#endif
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#ifdef CONFIG_SPI
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static struct module_pin_mux spi0_pin_mux[] = {
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{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
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{OFFSET(spi0_d0), MODE(0) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI0_D0 */
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{OFFSET(spi0_d1), MODE(0) | PULLUDEN |
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RXACTIVE}, /*SPI0_D1 */
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{OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, /*SPI0_CS0 */
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{-1},
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};
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static struct module_pin_mux spi1_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), MODE(4) | PULLUDEN | RXACTIVE}, /*SPI1_SCLK */
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{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI1_D0 */
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{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI1_D1 */
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{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI1_CS0 */
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{-1},
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};
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#endif
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/*
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* Update the structure with the modules present in the general purpose
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* board and the profiles in which the modules are present.
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* If the module is physically present but if it is not available
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* in any of the profile, then do not update it.
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* For eg, nand is avialable only in the profiles 0 and 1, whereas
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* UART0 is available in all the profiles.
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*/
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static struct evm_pin_mux general_purpose_evm_pin_mux[] = {
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{uart0_pin_mux, PROFILE_ALL},
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{i2c1_pin_mux, PROFILE_ALL},
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{i2c2_pin_mux, PROFILE_ALL},
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#ifdef CONFIG_NAND
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{nand_pin_mux, PROFILE_ALL},
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#endif
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#ifndef CONFIG_NO_ETH
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{rgmii1_pin_mux, PROFILE_ALL},
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//{rgmii1_pin_mux, PROFILE_1},
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//{rgmii2_pin_mux, PROFILE_0},
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#endif
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#ifdef CONFIG_MMC
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{mmc0_pin_mux, PROFILE_ALL},
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// {mmc1_pin_mux, PROFILE_2},
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#endif
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#ifdef CONFIG_SPI
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{spi0_pin_mux, PROFILE_0},
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{spi1_pin_mux, PROFILE_0},
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#endif
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// new io pins
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{sandia_pin_mux, PROFILE_ALL},
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{0},
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};
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|
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static struct evm_pin_mux *am335x_pin_mux[] = {
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general_purpose_evm_pin_mux,
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};
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/*
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* Configure the pin mux for the module
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*/
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static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
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{
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int i;
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|
|
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for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
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{
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|
/* #define DEBUG_PINMUX */
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|
#ifdef DEBUG_PINMUX
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printf("PINMUX[%d]:%04x - 0x%08x\n",i,mod_pin_mux[i].reg_offset, mod_pin_mux[i].val);
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|
#endif // DEBUG_PINMUX
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MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
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|
}
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|
}
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|
|
|
|
|
/*
|
|
* Check each module in the daughter board(first argument) whether it is
|
|
* available in the selected profile(second argument). If the module is not
|
|
* available in the selected profile, skip the corresponding configuration.
|
|
*/
|
|
static void set_evm_pin_mux(struct evm_pin_mux *pin_mux,
|
|
int prof)
|
|
{
|
|
int i;
|
|
|
|
if (!pin_mux)
|
|
return;
|
|
|
|
/*
|
|
* Only General Purpose & Industrial Auto Motro Control
|
|
* EVM has profiles. So check if this evm has profile.
|
|
* If not, ignore the profile comparison
|
|
*/
|
|
|
|
/*
|
|
* If the device is on baseboard, directly configure it. Else (device on
|
|
* Daughter board), check if the daughter card is detected.
|
|
*/
|
|
|
|
for (i = 0; pin_mux[i].mod_pin_mux != 0; i++) {
|
|
if ((pin_mux[i].profile & prof) ||
|
|
(prof == PROFILE_NONE)) {
|
|
configure_module_pin_mux(pin_mux[i].
|
|
mod_pin_mux);
|
|
}
|
|
}
|
|
}
|
|
|
|
void configure_evm_pin_mux(unsigned char profile)
|
|
{
|
|
set_evm_pin_mux(am335x_pin_mux[0], profile);
|
|
}
|
|
|
|
void enable_mmc0_pin_mux(void)
|
|
{
|
|
#ifdef CONFIG_MMC
|
|
configure_module_pin_mux(mmc0_pin_mux);
|
|
#endif
|
|
}
|
|
void enable_i2c0_pin_mux(void)
|
|
{
|
|
configure_module_pin_mux(i2c0_pin_mux);
|
|
}
|
|
|
|
void enable_i2c1_pin_mux(void)
|
|
{
|
|
configure_module_pin_mux(i2c1_pin_mux);
|
|
}
|
|
void enable_i2c2_pin_mux(void)
|
|
{
|
|
configure_module_pin_mux(i2c2_pin_mux);
|
|
}
|
|
|
|
void enable_sandia_pin_mux(void)
|
|
{
|
|
configure_module_pin_mux(sandia_pin_mux);
|
|
}
|
|
|
|
void enable_uart0_pin_mux(void)
|
|
{
|
|
configure_module_pin_mux(uart0_pin_mux);
|
|
}
|