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-- Company: ASTM/OmegaTi
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-- Engineer:Michele Canepa
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-- Module Name:acq_eng_seq_top.vhd
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-- Arch: Behavioral
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-- Acquisition Engine, top module, suitable to interface PulSAR family ADC's from
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-- Analog Devices. Includes a Block RAM to store the data coming from the ADC, the
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-- ADC interface, and the Address Generator.
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-- Done signal from ADC interface and write enable has a clock cycle latency, in order
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-- to let the address increment after writing on the RAM.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity acq_eng_seq_top is
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port(
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-- SPI ADC Interface Signals
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o_sclk: out std_logic;
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i_miso: in std_logic;
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i_busy: in std_logic;
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-- Emif Clock
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ema_clk: in std_logic;
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-- To CPU Interrupt Lines: end of frame signals
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o_eofa : out std_logic;
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o_eofb : out std_logic;
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--From Acq Controller
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i_framedepth: in std_logic_vector(2 downto 0);
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i_rst: in std_logic;
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i_cs: in std_logic;
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-- Memory Interface Signals
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i_addrb : in std_logic_vector(9 downto 0);
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i_conv: in std_logic;
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o_datab : out std_logic_vector(15 downto 0);
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done: out std_logic;
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shift_en: out std_logic-- Debug signal
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);
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end acq_eng_seq_top;
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architecture Behavioral of acq_eng_seq_top is
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component spi_core_seq is
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Port ( CLOCK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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MISO : in STD_LOGIC;
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SCLK : out STD_LOGIC;
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PARALLEL_OUT : out STD_LOGIC_VECTOR(15 downto 0);
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DONE: out std_logic;
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SHIFT_EN: out std_logic;-- Debug signal
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CONV_INPUT: in std_logic);
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end component;
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component spi_addrgen is
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port ( clk: in std_logic;
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done : in std_logic;
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rst: in std_logic;
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eofa : out std_logic;
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eofb : out std_logic;
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addr : out std_logic_vector (9 downto 0);
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frame_depth: in std_logic_vector(2 downto 0)
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);
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end component;
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component memory
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port (
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clka : in std_logic;
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wea : in std_logic_vector(0 downto 0);
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addra : in std_logic_vector(9 downto 0);
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dina : in std_logic_vector(15 downto 0);
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clkb : in std_logic;
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addrb : in std_logic_vector(9 downto 0);
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doutb : out std_logic_vector(15 downto 0)
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);
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end component;
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signal t_done: std_logic_vector(0 downto 0):=(others=>'0');
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signal t_wea: std_logic_vector(0 downto 0):=(others=>'0');
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signal t_datarx:std_logic_vector(15 downto 0);
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signal t_addra:std_logic_vector(9 downto 0);
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signal t_dataout:std_logic_vector(15 downto 0);
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signal eofa_r: std_logic:='0'; -- Per introdurre ritardo su end of frame
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signal eofb_r: std_logic:='0';
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begin
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spi_core_inst: spi_core_seq port map(
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CLOCK => ema_clk,
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RESET=> i_rst,
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MISO => i_miso,
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SCLK => o_sclk,
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PARALLEL_OUT=>t_datarx,
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DONE=>t_done(0),
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SHIFT_EN=>shift_en, -- Debug signal
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CONV_INPUT=>i_conv
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);
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spi_addrgen_inst: spi_addrgen PORT MAP(
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clk => ema_clk,
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done => t_wea(0), -- One-cycle delayed after t_done.
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rst => i_rst,
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eofa => eofa_r,
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eofb => eofb_r,
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addr => t_addra,
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frame_depth => i_framedepth
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);
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MEMORY_inst : MEMORY
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PORT MAP (
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clka => ema_clk,
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wea => t_done,
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addra => t_addra,
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dina => t_datarx,
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clkb => ema_clk,
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addrb => i_addrb,
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doutb => t_dataout
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);
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-- A flip-flop to delay t_wea signal in respect to t_done signal.
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wea_dly: process(ema_clk,t_done)
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begin
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if rising_edge(ema_clk) then
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t_wea<=t_done;
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end if;
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end process;
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-- End of frame flip-flop to delay.
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eof_dly: process(ema_clk, eofa_r, eofb_r)
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begin
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if rising_edge(ema_clk) then
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o_eofa<=eofa_r;
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o_eofb<=eofb_r;
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end if;
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end process;
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-- This process synchronizes readings and implements chip select.
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reg_read: process(ema_clk)
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begin
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if rising_edge(ema_clk) then
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if i_cs = '1' then
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o_datab <= t_dataout;
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else
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o_datab <= (others=>'0');
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end if;
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end if;
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end process;
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-- Done is a single signal, t_done is a vector(0 downto 0)
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done<=t_done(0);
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end Behavioral;
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