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--- Title: EMIFA_ifaceMC.vhd
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--- Description:
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---
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--- EMIFA interface for OMAP-L138 series CPU platform MODIFIED BY MICHELE CANEPA
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--- Date: 18/04/2013
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--- Version: 1.00
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--- Revisions:
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--- 1.00 - Baseline.
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library WORK;
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library IEEE;
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library UNISIM;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use UNISIM.VCOMPONENTS.ALL;
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use WORK.MityDSP_L138_pkg.ALL;
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entity EMIFA_ifaceMC is
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generic (
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DECODE_BITS : integer range 1 to 9 := 5;
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DECODE_BITS4 : integer range 1 to 5 := 5; -- Custom decode bits. Address space is CS4
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. CONFIG : string := "UNKNOWN" -- "MityDSP_L138"
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);
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port (
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ema_clk : in std_logic; -- conditioned by a DCM
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-- EMIFA direct-connect signals
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i_ema_cs0_n : in std_logic; -- Reserved for SDRAM controller, not used
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i_ema_cs2_n : in std_logic; -- Reserved core space, not used
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i_ema_cs3_n : in std_logic; -- NAND FLASH space, not used
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i_ema_cs4_n : in std_logic; -- Any CPU core space
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i_ema_cs5_n : in std_logic; -- Any CPU core space
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i_ema_oe_n : in std_logic;
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i_ema_we_n : in std_logic;
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o_ema_wait_n : out std_logic_vector(1 downto 0);
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t_ema_wait : out std_logic;
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i_ema_d : in std_logic_vector(15 downto 0);
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o_ema_d : out std_logic_vector(15 downto 0);
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t_ema_d : out std_logic;
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i_ema_a : in std_logic_vector(13 downto 0);
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i_ema_ba : in std_logic_vector(1 downto 0);
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i_ema_wen_dqm : in std_logic_vector(1 downto 0);
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i_ema_cas : in std_logic; -- reserved for SDRAM controller, not used
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i_ema_ras : in std_logic; -- reserved for SDRAM controller, not used
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i_ema_sdcke : in std_logic; -- reserved for SDRAM controller, not used
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i_ema_rnw : in std_logic; -- reserved for SDRAM controller, not used
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-- FPGA core interface signals
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o_core_be : out std_logic_vector(1 downto 0);
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o_core_addr : out std_logic_vector(5 downto 0);
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o_core_addr4 : out std_logic_vector(9 downto 0);--Added to give 10 bits addressing.
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o_core_cs5 : out std_logic_vector((2**DECODE_BITS)-1 downto 0);
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o_core_cs4 : out std_logic_vector((2**DECODE_BITS4)-1 downto 0);-- Decode bits are custom.
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o_core_edi : out std_logic_vector(15 downto 0);
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i_core_edo5 : in bus16_vector((2**DECODE_BITS)-1 downto 0);
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i_core_edo4 : in bus16_vector((2**DECODE_BITS)-1 downto 0);
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o_core_rd : out std_logic;
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o_core_wr : out std_logic
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);
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end EMIFA_ifaceMC;
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architecture rtl of EMIFA_ifaceMC is
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signal be : std_logic_vector(1 downto 0) := (others=>'1');
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signal ea : std_logic_vector(14 downto 0) := (others=>'0');
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signal cs5_n : std_logic := '1';
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signal cs4_n : std_logic := '1';
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signal oe_n : std_logic := '1';
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signal we_n : std_logic := '1';
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signal oe_dly : std_logic := '1';
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signal we_dly : std_logic := '1';
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signal edi : std_logic_vector(15 downto 0);
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-- Caution! Despite disabling shift-register extraction on these signals,
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-- setting Global Optimization in Map can still optimize them back into SRL's.
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attribute shreg_extract : string;
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attribute shreg_extract of be : signal is "no";
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attribute shreg_extract of ea : signal is "no";
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attribute shreg_extract of edi : signal is "no";
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signal cs5 : std_logic_vector((2**DECODE_BITS)-1 downto 0) := (others=>'0');
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signal cs4 : std_logic_vector((2**DECODE_BITS4)-1 downto 0) := (others=>'0');-- Modified decode bits
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signal rd : std_logic := '0';
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signal wr : std_logic := '0';
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signal ema_d : std_logic_vector(15 downto 0) := (others=>'0');
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attribute shreg_extract of ema_d : signal is "no";
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begin -- architecture: rtl
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-- register input signals
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process (ema_clk)
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begin
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if rising_edge(ema_clk) then
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-- capture byte-enables and address bus
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be <= i_ema_wen_dqm;
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ea <= i_ema_a & i_ema_ba(1);
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-- capture control signals
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cs5_n <= i_ema_cs5_n; -- These control signals are NOT inverted here
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cs4_n <= i_ema_cs4_n; -- so that the registers can be packed into IOB's.
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oe_n <= i_ema_oe_n;
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we_n <= i_ema_we_n;
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-- one-clock delayed registers
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oe_dly <= oe_n;
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we_dly <= we_n;
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-- capture the data bus
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edi <= i_ema_d;
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end if;
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end process;
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-- address decode, ARM chip select space
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process (cs5_n, ea)
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begin
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if cs5_n='0' then
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for count in 0 to (2**DECODE_BITS)-1 loop
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if ea(DECODE_BITS+5 downto 6) = conv_std_logic_vector(count, DECODE_BITS) then
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cs5(count) <= '1';
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else
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cs5(count) <= '0';
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end if;
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end loop;
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else
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cs5 <= (others=>'0');
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end if;
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end process;
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-- address decode, DSP chip select space, modified to be 1024 addresses per module.
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process (cs4_n, ea)
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begin
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if cs4_n='0' then
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for count in 0 to (2**DECODE_BITS4)-1 loop
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if ea(DECODE_BITS4 +9 downto 10) = conv_std_logic_vector(count, DECODE_BITS4) then
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cs4(count) <= '1';
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else
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cs4(count) <= '0';
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end if;
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end loop;
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else
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cs4 <= (others=>'0');
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end if;
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end process;
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-- read/write strobes
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rd <= oe_n and not oe_dly;
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wr <= not we_n and we_dly;
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-- register output signals
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process (ema_clk)
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begin
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if rising_edge(ema_clk) then
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o_core_be <= not be; -- invert to positive logic
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o_core_addr <= ea(5 downto 0);
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o_core_addr4<= ea(9 downto 0); --Modified to 10 bit.
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o_core_cs5 <= cs5;
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o_core_cs4 <= cs4;
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o_core_rd <= rd;
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o_core_wr <= wr;
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o_core_edi <= edi;
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end if;
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end process;
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-- multiplex module data-out busses
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process (ema_clk)
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variable ored : std_logic_vector(15 downto 0);
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begin
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if rising_edge(ema_clk) then
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ored := x"0000";
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for count in 0 to (2**DECODE_BITS)-1 loop
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ored := ored or i_core_edo5(count) or i_core_edo4(count);
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end loop;
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ema_d <= ored; -- TODO - mux in other "custom" CS spaces???
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o_ema_d <= ema_d; -- extra clock should allow packing in IOB
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end if;
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end process;
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t_ema_d <= '0' when (i_ema_oe_n='0' and (i_ema_cs5_n='0' or i_ema_cs4_n='0')) else '1';
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t_ema_wait <= '1';
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end rtl;
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