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--- Title:IndustrialIO_top.vhd
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--- Description:
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---
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--- o 0
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--- | / Copyright (c) 2010
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--- (CL)---o Critical Link, LLC
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--- \
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--- O
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---
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--- Company: Critical Link, LLC.
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--- Date: 03/7/2010
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--- Version: 1.20
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---
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--- Revision History
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--- 1.00 - Initial revision
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--- 1.10 - REVISION TO AGREE WITH CUSTOM BOARD ANALOG1
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--- 1.20 - REVISION FOLLOWING GREGORY GLUSZEK (CL) SUGGESTIONS about GPIOS.
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library WORK;
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library IEEE;
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library UNISIM;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use UNISIM.VCOMPONENTS.ALL;
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use WORK.MityDSP_L138_pkg.ALL;
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entity PQMUIO_top is
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generic ( BOARD_REV : string := "C"; -- "A", "B", or "C"
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DECODE_BITS : integer range 1 to 9 := 9;
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CAMERA_CONFIG : string := "NONE"; -- "RAW" - route camera I/O hack to RAW Video input interface
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DISP_CONFIG : string := "LCD"; -- "LCD", "DVI" or "NONE"
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LCD_TYPE : string := "SHARP" -- "SHARP" or "NEC"
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);
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port (
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i_ema_clk : in std_logic; -- 100 MHz EMIF clock
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-- DSP EMIFA BUS Interface
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i_ema_cs0_n : in std_logic; -- RESERVED for SDRAM Controller
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i_ema_cs2_n : in std_logic; -- ARM core CE space
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i_ema_cs3_n : in std_logic; -- NAND FLASH space, not used
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i_ema_cs4_n : in std_logic; -- DSP core CE space
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i_ema_cs5_n : in std_logic; -- Reserved core space, not used
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i_ema_oe_n : in std_logic;
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i_ema_we_n : in std_logic;
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io_ema_wait_n : inout std_logic_vector(1 downto 0);
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io_ema_d : inout std_logic_vector(15 downto 0);
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i_ema_a : in std_logic_vector(13 downto 0);
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i_ema_ba : in std_logic_vector(1 downto 0);
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i_ema_wen_dqm : in std_logic_vector(1 downto 0);
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i_ema_cas : in std_logic; -- reserved for SDRAM controller, not used
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i_ema_ras : in std_logic; -- reserved for SDRAM controller, not used
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i_ema_sdcke : in std_logic; -- reserved for SDRAM controller, not used
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i_ema_rnw : in std_logic; -- reserved for SDRAM controller, not used
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-- DSP IRQ lines
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o_nmi_n : out std_logic;
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o_int : out std_logic_vector(1 downto 0);
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-- dac cal&offset control signals
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o_dac_cal_ctrl: out std_logic_vector(5 downto 0);
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-- ext gpio control signals
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o_ext_gpio: out std_logic_vector(1 downto 0);
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-- ia write enable signals
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o_ia_wr: out std_logic_vector(3 downto 0);
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-- channel configuration control signals
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o_chann_config: out std_logic_vector(2 downto 0);
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-- FSPI_1 signals
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o_fspi1_mosi: out std_logic;
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i_fspi1_miso: in std_logic;
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o_fspi1_clk: out std_logic;
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o_fspi1_cs: out std_logic_vector (7 downto 0);
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-- FSPI_2 signals
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o_fspi2_mosi: out std_logic;
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i_fspi2_miso: in std_logic;
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o_fspi2_clk: out std_logic;
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o_fspi2_cs: out std_logic_vector (7 downto 0);
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-- sampling clock manager
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i_from_out_conv: in std_logic;
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o_to_in_conv: out std_logic
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);
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end PQMUIO_top;
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architecture rtl of PQMUIO_top is
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...
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...
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--NEW SIGNALS I ADDED
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signal s_dac_cal_ctrl : std_logic_vector(5 downto 0);
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signal s_ext_gpio : std_logic_vector(1 downto 0);
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signal s_ia_wr : std_logic_vector(3 downto 0);
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signal s_chann_config : std_logic_vector(2 downto 0);
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begin -- architecture: rtl
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-------------------------------------------------------------------------
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-- DAC CALIBRATION CONTROL GPIO CORE
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-------------------------------------------------------------------------
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dac_cal_ctrl_inst: gpio
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generic map(
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NUM_BANKS => 1,
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NUM_IO_PER_BANK =>6
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)
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port map(
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clk => ema_clk,
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i_ABus => addr_r,
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i_DBus => edi_r,
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o_DBus => edo_arm(CORE_DAC_CAL_CTRL_MODULE),
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i_wr_en => wr_r,
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i_rd_en => rd_r,
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i_cs => arm_cs5_r(CORE_DAC_CAL_CTRL_MODULE),
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o_irq => irq_map(CORE_DAC_CAL_CTRL_IRQ_LEVEL)(CORE_DAC_CAL_CTRL_IRQ_VECTOR),
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i_ilevel => conv_std_logic_vector(CORE_DAC_CAL_CTRL_IRQ_LEVEL, 2),
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i_ivector => conv_std_logic_vector(CORE_DAC_CAL_CTRL_IRQ_VECTOR, 4),
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i_io => s_dac_cal_ctrl, -- GPIO read values. Loop back output values so they can be read from software.
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t_io => open,-- Do not care about direction of GPIOs
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o_io => s_dac_cal_ctrl,-- GPIO write value
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i_initdir => "111111",
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i_initoutval => "000000"
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);
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o_dac_cal_ctrl <= s_dac_cal_ctrl;
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...
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...
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end rtl;
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