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/**
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* \file regs_upp.h
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*
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* \brief Register information for the uPP device.
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*
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* o 0
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* | / Copyright (c) 2005-2010
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* (CL)---o Critical Link, LLC
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* \
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* O
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*/
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#ifndef _REGS_UPP_H_
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#define _REGS_UPP_H_
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#include <stdint.h>
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////////////////////////////////////////////////////////////////////////////
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/// @struct tsUppRegs tsUppRegs.h "core/tsUppRegs.h"
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/// Private structure for uPP Control Registers.
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////////////////////////////////////////////////////////////////////////////
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struct tsUppRegs
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{
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volatile uint32_t UPPID; // 0x00 uPP Peripheral Identification Register Section 3.1
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volatile uint32_t UPPCR; // 0x04 uPP Peripheral Control Register Section 3.2
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volatile uint32_t UPDLB; // 0x08 uPP Digital Loopback Register Section 3.3
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volatile uint32_t EMPT0; // 0x0C
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volatile uint32_t UPCTL; // 0x10 uPP Channel Control Register Section 3.4
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volatile uint32_t UPICR; // 0x14 uPP Interface Configuration Register Section 3.5
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volatile uint32_t UPIVR; // 0x18 uPP Interface Idle Value Register Section 3.6
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volatile uint32_t UPTCR; // 0x1C uPP Threshold Configuration Register Section 3.7
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volatile uint32_t UPISR; // 0x20 uPP Interrupt Raw Status Register Section 3.8
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volatile uint32_t UPIER; // 0x24 uPP Interrupt Enabled Status Register Section 3.9
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volatile uint32_t UPIES; // 0x28 uPP Interrupt Enable Set Register Section 3.10
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volatile uint32_t UPIEC; // 0x2C uPP Interrupt Enable Clear Register Section 3.11
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volatile uint32_t UPEOI; // 0x30 uPP End-of-Interrupt Register Section 3.12
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volatile uint32_t EMPT1; // 0x34
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volatile uint32_t EMPT2; // 0x38
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volatile uint32_t EMPT3; // 0x3C
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volatile uint32_t UPID0; // 0x40 uPP DMA Channel I Descriptor 0 Register Section 3.13
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volatile uint32_t UPID1; // 0x44 uPP DMA Channel I Descriptor 1 Register Section 3.14
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volatile uint32_t UPID2; // 0x48 uPP DMA Channel I Descriptor 2 Register Section 3.15
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volatile uint32_t EMPT4; // 0x4C
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volatile uint32_t UPIS0; // 0x50 uPP DMA Channel I Status 0 Register Section 3.16
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volatile uint32_t UPIS1; // 0x54 uPP DMA Channel I Status 1 Register Section 3.17
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volatile uint32_t UPIS2; // 0x58 uPP DMA Channel I Status 2 Register Section 3.18
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volatile uint32_t EMPT5; // 0x5C
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volatile uint32_t UPQD0; // 0x60 uPP DMA Channel Q Descriptor 0 Register Section 3.19
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volatile uint32_t UPQD1; // 0x64 uPP DMA Channel Q Descriptor 1 Register Section 3.20
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volatile uint32_t UPQD2; // 0x68 uPP DMA Channel Q Descriptor 2 Register Section 3.21
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volatile uint32_t EMPT6; // 0x6C
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volatile uint32_t UPQS0; // 0x70 uPP DMA Channel Q Status 0 Register Section 3.22
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volatile uint32_t UPQS1; // 0x74 uPP DMA Channel Q Status 1 Register Section 3.23
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volatile uint32_t UPQS2; // 0x78 uPP DMA Channel Q Status 2 Register Section 3.24
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};
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union tuUppcrReg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t FREE : 1;
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uint32_t SOFT : 1;
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uint32_t RTEMU : 1;
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uint32_t EN : 1;
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uint32_t SWRST : 1;
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uint32_t RSVD0 : 2;
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uint32_t DB : 1;
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uint32_t RSVD1 : 24;
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} sRegBits;
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};
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union tuUpctlReg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t MODE : 2;
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uint32_t CHN : 1;
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uint32_t SDRTXIL : 1;
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uint32_t DDRDEMUX : 1;
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uint32_t RSVD0 : 11;
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uint32_t DRA : 1;
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uint32_t IWA : 1;
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uint32_t DPWA : 3;
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uint32_t DPFA : 2;
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uint32_t RSVD1 : 1;
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uint32_t DRB : 1;
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uint32_t IWB : 1;
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uint32_t DPWB : 3;
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uint32_t DPFB : 2;
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uint32_t RSVD2 : 1;
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} sRegBits;
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};
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// MODE bits in UPCTL register.
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enum teUppMode
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{
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eeAllRcv = 0,
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eeAllXmit = 1,
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eeARcvBXmit = 2,
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eeAXmitBRcv = 3
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};
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// Data Packing Format. DPFA and DPFB bits in UPCTL register.
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enum teUppDpf
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{
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eeRJZE = 0, // Right-justified, zero extended
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eeRJSE = 1, // Right-justified, sign extended
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eeLJZF = 2 // Left-justified, zero filled
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};
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union tuUpicrReg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t STARTPOLA : 1;
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uint32_t ENAPOLA : 1;
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uint32_t WAITPOLA : 1;
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uint32_t STARTA : 1;
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uint32_t ENAA : 1;
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uint32_t WAITA : 1;
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uint32_t RSVD0 : 2;
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uint32_t CLKDIVA : 4;
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uint32_t CLKINVA : 1;
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uint32_t TRISA : 1;
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uint32_t RSVD1 : 2;
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uint32_t STARTPOLB : 1;
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uint32_t ENAPOLB : 1;
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uint32_t WAITPOLB : 1;
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uint32_t STARTB : 1;
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uint32_t ENAB : 1;
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uint32_t WAITB : 1;
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uint32_t RSVD2 : 2;
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uint32_t CLKDIVB : 4;
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uint32_t CLKINVB : 1;
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uint32_t TRISB : 1;
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uint32_t RSVD3 : 2;
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} sRegBits;
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};
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union tuUpivrReg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t VALA : 16;
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uint32_t VALB : 16;
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} sRegBits;
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};
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union tuUptcrReg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t RDSIZEI : 2;
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uint32_t RSVD0 : 6;
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uint32_t RDSIZEQ : 2;
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uint32_t RSVD1 : 6;
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uint32_t TXSIZEA : 2;
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uint32_t RSVD2 : 6;
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uint32_t TXSIZEB : 2;
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uint32_t RSVD3 : 6;
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} sRegBits;
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};
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union tuUpisrReg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t DPEI : 1;
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uint32_t UORI : 1;
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uint32_t ERRI : 1;
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uint32_t EOWI : 1;
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uint32_t EOLI : 1;
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uint32_t RSVD0 : 3;
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uint32_t DPEQ : 1;
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uint32_t UORQ : 1;
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uint32_t ERRQ : 1;
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uint32_t EOWQ : 1;
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uint32_t EOLQ : 1;
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uint32_t RSVD1 : 19;
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} sRegBits;
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};
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typedef tuUpisrReg tuUpierReg;
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typedef tuUpisrReg tuUpiesReg;
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typedef tuUpisrReg tuUpiecReg;
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union tuUpiqd1Reg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t BCNT : 16;
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uint32_t LNCNT : 16;
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} sRegBits;
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};
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union tuUpiqs2Reg
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{
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uint32_t nRegWord;
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struct
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{
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uint32_t ACT : 1;
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uint32_t PEND : 1;
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uint32_t RSVD0 : 2;
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uint32_t WM : 4;
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uint32_t RSVD1 : 24;
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} sRegBits;
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};
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#endif
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