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DDR configuration for AISgen on MityDSP-L138 ยป MityDSP.cfg

AISgen config file - Friedrich Feichtinger, 04/26/2016 09:14 AM

 
Boot Mode=SPI1 Flash
Boot Speed=1
Flash Width=1
Flash Timing=3ffffffd
Configure Peripheral=True
Configure PLL0=True
Configure SDRAM=False
Configure PLL1=True
Configure DDR2=True
Configure LPSC=False
Configure Pinmux=False
Enable CRC=False
Specify Entrypoint=False
Enable Sequential Read=False
Use 4.5 Clock Divider=False
Use DDR2 Direct Clock=False
Use mDDR=True
Use DuplicateMddrSetting=True
ROM ID=3
Device Type=1
Input Clock Speed=24
Clock Type=1
PLL0 Pre Divider=1
PLL0 Multiplier=19
PLL0 Post Divider=1
PLL0 Div1=1
PLL0 Div3=5
PLL0 Div7=12
PLL1 Multiplier=25
PLL1 Post Divider=2
PLL1 Div1=1
PLL1 Div2=2
PLL1 Div3=3
Entrypoint=c1080000
SDRAM SDBCR=0
SDRAM SDTMR=0
SDRAM SDRSRPDEXIT=0
SDRAM SDRCR=0
DDR2 PHY=c5
DDR2 SDCR=620
DDR2 SDCR2=0
DDR2 SDTIMR=1c912a08
DDR2 SDTIMR2=3811c700
DDR2 SDRCR=4e2
LPSC0 Enable=
LPSC0 Disable=
LPSC0 SyncRst=
LPSC1 Enable=13+
LPSC1 Disable=
LPSC1 SyncRst=
Pinmux=
App File String=C:\LED_ARM_MyDSP.out;C:\MityDSP_LED_blink.out
AIS File Name=C:\Users\Gahli\Desktop\MityDSP_LED_blink.bin
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